1. Field of the Invention
This invention relates to the field of digital electronics, and in particular to a timing circuit for generating clock signals from a reference signal, particularly for use in digital networks.
2. Description of Related Art
Timing circuits are used for a numerous clocking applications, particularly in digital communications networks. A typical timing circuit comprises a phase locked loop, particularly a digital phase locked loop in which the output of a digital controlled oscillator, divided by a number n, is fed back to a digital phase detector and compared with the input signal. The output of the phase detector is fed to the input of the digital controlled oscillator through a digital filter.
In typical PLL architectures the output of the PLL is never precisely identical to its input. If the input is steady the output may closely follow the input, but will have a slightly different behavior due to noise. In case the input is not steady, the PLL will try to follow the noise, but necessarily with a relatively late response. In PLL's there is typically no basis on which the future value of the input signal can be predicted. Consequently non-causal filtering is required to accurately track the input signal, which clearly is impossible. If accurate analog delay means were feasible it might be possible to precisely mimic the delayed input. However, this type of behavior only exists for signal restoration, where the input signal has information, for example, concerning the phase or frequency domain. This may be the case for receivers, where the PLL forms a convoluter that establishes highest accuracy when the signal is most accurately followed.
In a large class of applications of PLL's, it is actually not desirable for the PLL to precisely follow the input signal. Instead the function of the PLL may be to follow the course behavior of the input signal, but at the same time lose certain aspects of the input signal. A typical example would be a PLL that has a low frequency pass characteristic, which allows for rejection of error components with a relatively high frequency. Another would be a PLL with a band suppression characteristic, which can be used to suppress a known and well quantifiable error such as 50 or 60 Hz spurious. These types of PLL all have the property that they intentionally lose information, and that the input signal and output signal are not identical, and probably not even nearly identical.
PLL's can also be categorized in a number of characteristics in their implementation. Two aspects that can be used, amongst others, are related to the input processing performed in the phase detector. The input may or may not use amplitude, time quantization or both on the input signal. Thus four classes of implementation arise, of which only one is truly digital; the implementation with time and amplitude quantization.
A conventional radio receiver utilizes no quantization in either time or amplitude in its first stages. The existence of many large disturbances will make amplitude quantization difficult due to the number of required bits; time quantization would lose details on for instance phase information. Instead the use of downconversion and sharp filtering on the generated IF frequency yields the effect of losing undesirable signals. The crucial element in this is that effectively the mixing element (which may be called phase detector) forms a simple convoluter to emphasize the desired signal.
Most phase detectors operate on amplitude discrete, time-continuous basis. The output of the phase detector behaves as an analog signal when looked at over some longer period. With a low pass filter the phase detector becomes truly analog. This is due to the time continuous inputs of the detector, and this translates into amplitude continuity on the output.
There are phase detectors, for instance for very high frequency radars, that operate on the basis of sampling the high frequency signal. By sampling over an extremely short period of time (sampling period of 5 ps is possible) the amplitude of the feedback signal or the reference signal is sampled. This avoids the necessity of dividers, and works well for the high frequencies where typically the generated signals more look like sinusoids than squares, which is essential for the linearity of the phase detector. The amplitude continuity here directly leads to phase detector output continuity.
In a truly digital phase detector it therefore will be clear that both the time and the amplitude aspect are discrete. This makes it possible to avoid analog elements, such as in the low pass filter, that inherently introduce all kinds of undesirable inaccuracies. A time discrete signal can be expressed accurately in a number of steps of error, which is the most important property. Fine amplitude quantization (small error) is not so extremely important, but it is essential to have at least information of two levels, so that it becomes relatively trivial to make the PLL go faster or slower. A finer time quantization makes the error in the quantization smaller, a finer amplitude quantization may help in more precisely establishing zero crossings by extrapolation, which also yields smaller time errors. Both error mechanisms can be expressed in equivalent phase error.
Now to implement a very accurate PLL as for instance used for 2.048 MHz signals, which are used in an ST-bus, it is desirable to have the error signal quantized as soon and accurately as possible. The reason for this stems from related accuracies and operations.
A telecomm PLL must have a stable and accurate low pass frequency. The margins that are allowable within the various standards are not extremely large, and become very small if one wants to fulfill several standards or variations within one device. Analog implementations typically suffer from production spread, which for instance within chips can run up to about 50% inaccuracy. A 100% integrated approach is much more robust when made in digital fashion.
An operation such as HOLDOVER (keep on generating some frequency even when the reference does not exist anymore) is a typical non-linear operation which requires memory. This can be implemented in analog fashion, but it is extremely difficult to achieve accuracies of for instance 1E-10. A normal analog implementation typically will already make a jump in either change, current or voltage of for instance 100 ppm. This would imply that the sensitivity of the VCO must be extremely low, which in turn heavily reduces the maximum frequency range, and necessitates a high initial VCO accuracy. To reduce for instance the inaccuracy of the jump relatively complex techniques must be used, such as digital-to-analog converters with many bits and quite possibly trimming. A fully digital implementation can switch virtually error free.
An operation such as switching between two references which are not necessarily in phase performed in analog systems, but requires a measurement/activation cycle, typically using analog-to-digital and digital-to-analog converters. On switching to the new reference any phase offset is handled so that the output phase appears to remain constant. In Analog solutions the realization of the offset is typically done by subtracting the offset at the output of the phase detector with a digital-to-analog convener. In a digital solution this operation is much simpler.
Flexibility is much greater in the digital domain. Non-linear operations such as changing the low pass frequency are quite straightforward to implement. In the analog domain these operations yield extra demands, which have a direct impact on accuracies.
The digital domain can be setup such that the accuracies come directly from the system frequency. If made with a crystal the accuracy is high due to the natural properties of the crystal, especially its high quality. An analog implementation can only use a high quality oscillator by utilizing a VCXO (Voltage Controlled Xtal oscillator), which directly limits its frequency range.
Digital implementations have no particular difficulty in combining high accuracies with large dynamic ranges. To continue with the analog example; a 20-bit accurate DAC still requires a VCO range of only 100 ppm to yield a HOLDOVER accuracy of 1E-10. A digital solution can easily supply a 25% or even 100% range with such a HOLDOVER.
In an all digital implementation the error signals will all be in digital format. This makes the use of these values in statistical measurements (average, min, max, mean, deviation etc) relatively trivial. In an analog solution the signals must be converted to digital first, or be handled with very difficult analog circuits. One of the difficult elements in the analog domain is that the signals may have a wildly varying dynamical range from signal to signal, which does not make the implementation simpler.
In short, an all digital implementation has many advantages. The accuracies that typically are required in telecomm standards almost force the use of digital approaches, especially when a completely integrated approach is desired. The flexibility of an all digital approach is then an extra that can be utilized to expand functionalities.
The functional block diagram of a digital solution is in fact hardly different from the normal analog case; only the blocks are implemented in a digital fashion, with multibit connections instead of analog signals in between. That makes the modeling of an analog PLL almost 100% applicable, which is a well known area from many publications.
An all digital P1 has one major drawback. The feedback signal and the reference typically will not be in Phase because the PLL suppresses certain signal artifacts. This lack of phase alignment directly translates to timing errors. The implicit sampling is discrete and therefore has rounding/trunking errors. This in itself may not seem too serious at a first glance, but it has a direct impact on the transfer function of the PLL, which is related to the transfer function of the phase detector.
An object of the invention is to alleviate the above noted problems present in the prior art.